UNIT-III Addressing modes & Instruction set

** Explain 8051 instruction set (or) classification of 8051 instruction set (or) types of instructions.

Depending on operation all instructions are divided in fivel groups:

· Data Transfer Instructions

· Arithmetic Instructions

· Logic Instructions

· Branch Instructions

· Bit-oriented Instructions (or) Boolean instructions.

Data Transfer instructions :

In 8051 microcontroller MOV,MOVC,MOVX,PUSH,POP,XCH and XCHD instructions are used to transfer data between registers and memory locations.

In 8051 microcontroller data transfer operations are :

—> Copy the content of a SFR to internal memory ( or) vice versa

—> Load an immediate operand to SFR/internal memory.

—> Exchange the content of SFR/internal memory with A.

—> Copy the content of program memory to Accumulator.

—> Copy the content of data memory to accumulator (or) vice versa.

Eg:- MOV A, R_nMOV A, direct MOV A, @ R_i MOV A, # Data.

Arithmetic Instructions :

In 8051 Microcontroller we perform addition, subtraction, multiplication, division, increment and decrement operations on binary data.

The mnemonic used for arithmetic operations are ADD,ADD C,SUB B, INC,DEC,MUL,DIV and DA.

The result of most of the arithmetic operation is stored in accumulator except a few decrement and increment operations, except increment and decrement instructions all other arithmetic instructions are effected (modify) the flags of 8051.

Eg: ADD A , R_n INC @ R₁ SUBB A, direct DEC R_nMUL AB DIV AB

Logical Instructions :

In 8051 microcontroller we performing logical AND, OR, EX-OR, Complement operations and right, left rotating operations.

The mnemonic used for logical operations are ANL, ORL, XRL, CLR, CPL, RL,RLC, RR, RRC and SWAP.

In logical operations only rotate through carry operation is effected the flags of 8051. In rotate through carry flag alone is modified (effected).

In most of the logical instructions the result is stored in accumulator and in some instructions the result is stored in internal RAM/SFR.

Eg: ANL A, R_n ORL A, # data RRC A SWAP A

Branch instructions :

Normally a program is executed sequentially an PC (program counter) keeps track of the address of instructions and it is incremented appropriately after each fetch operation.

The program branching instructions will modify the content of PC. So that the program control branches to a new address.

There are two types of program branching instructions.

1. Conditional branching instructions.

2. Un conditional branching instructions.

In conditional branching instructions the content of PC is modified only if the condition specified in the instruction is true, where as in unconditional branching instruction the PC is always modified.

The instructions like A CALL & L CALL will save the previous value of PC in stack before modifying the PC.

Eg: JNZ offset JZ offset LJUMP 16-bit RET NOP DJNZ R_n, offset.

Boolean Variable instructions :

The Boolean variable instructions operate on a particular bit of a data. This group include instructions which clear, complement or move a particular bit of bit addressable RAM/SFR (or) carry flag.

It also include jump instructions which transfer the program control to a new address if a particular bit is set or cleared. The Boolean variable instructions of 8051 are

Eg: CLR C SETB C SETB bit CPL C CPL bit MOV C,bit JC offset JNC etc.

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Notes on instructions.:

The first part of each instruction, called MNEMONIC refers to the operation an instruction performs (copy, addition, logic operation etc.). Mnemonics are abbreviations of the name of operation being executed. For example:

INC
R1

– Means: Increment register R1 (increment register R1);

· LJMP LAB5 – Means: Long Jump LAB5 (long jump to the address marked as LAB5);

· JNZ LOOP – Means: Jump if Not Zero LOOP (if the number in the accumulator is not 0, jump to the address marked as LOOP);

The other part of instruction, called OPERAND is separated from mnemonic by at least one whitespace and defines data being processed by instructions. Some of the instructions have no operand, while some of them have one, two or three. If there is more than one operand in an instruction, they are separated by a comma. For example:

· RET – return from a subroutine;

· JZ TEMP – if the number in the accumulator is not 0, jump to the address marked as TEMP;

· ADD A,R3 – add R3 and accumulator;

· CJNE A,#20,LOOP – compare accumulator with 20. If they are not equal, jump to the address marked as LOOP;

Arithmetic instructions

Arithmetic instructions perform several basic operations such as addition, subtraction, division, multiplication etc. After execution, the result is stored in the first operand. For example:

ADD A,R1 – The result of addition (A+R1) will be stored in the accumulator.

ARITHMETIC INSTRUCTIONS
Mnemonic	Description	Byte	Cycle
ADD A,Rn	Adds the register to the accumulator	1	1
ADD A,direct	Adds the direct byte to the accumulator	2	2
ADD A,@Ri	Adds the indirect RAM to the accumulator	1	2
ADD A,#data	Adds the immediate data to the accumulator	2	2
ADDC A,Rn	Adds the register to the accumulator with a carry flag	1	1
ADDC A,direct	Adds the direct byte to the accumulator with a carry flag	2	2
ADDC A,@Ri	Adds the indirect RAM to the accumulator with a carry flag	1	2
ADDC A,#data	Adds the immediate data to the accumulator with a carry flag	2	2
SUBB A,Rn	Subtracts the register from the accumulator with a borrow	1	1
SUBB A,direct	Subtracts the direct byte from the accumulator with a borrow	2	2
SUBB A,@Ri	Subtracts the indirect RAM from the accumulator with a borrow	1	2
SUBB A,#data	Subtracts the immediate data from the accumulator with a borrow	2	2
INC A	Increments the accumulator by 1	1	1
INC Rn	Increments the register by 1	1	2
INC Rx	Increments the direct byte by 1	2	3
INC @Ri	Increments the indirect RAM by 1	1	3
DEC A	Decrements the accumulator by 1	1	1
DEC Rn	Decrements the register by 1	1	1
DEC Rx	Decrements the direct byte by 1	1	2
DEC @Ri	Decrements the indirect RAM by 1	2	3
INC DPTR	Increments the Data Pointer by 1	1	3
MUL AB	Multiplies A and B	1	5
DIV AB	Divides A by B	1	5
DA A	Decimal adjustment of the accumulator according to BCD code	1	1

Branch Instructions

There are two kinds of branch instructions:

Unconditional jump instructions: upon their execution a jump to a new location from where the program continues execution is executed.

Conditional jump instructions: a jump to a new program location is executed only if a specified condition is met. Otherwise, the program normally proceeds with the next instruction.

BRANCH INSTRUCTIONS
Mnemonic	Description	Byte	Cycle
ACALL addr11	Absolute subroutine call	2	6
LCALL addr16	Long subroutine call	3	6
RET	Returns from subroutine	1	4
RETI	Returns from interrupt subroutine	1	4
AJMP addr11	Absolute jump	2	3
LJMP addr16	Long jump	3	4
SJMP rel	Short jump (from –128 to +127 locations relative to the following instruction)	2	3
JC rel	Jump if carry flag is set. Short jump.	2	3
JNC rel	Jump if carry flag is not set. Short jump.	2	3
JB bit,rel	Jump if direct bit is set. Short jump.	3	4
JBC bit,rel	Jump if direct bit is set and clears bit. Short jump.	3	4
JMP @A+DPTR	Jump indirect relative to the DPTR	1	2
JZ rel	Jump if the accumulator is zero. Short jump.	2	3
JNZ rel	Jump if the accumulator is not zero. Short jump.	2	3
CJNE A,direct,rel	Compares direct byte to the accumulator and jumps if not equal. Short jump.	3	4
CJNE A,#data,rel	Compares immediate data to the accumulator and jumps if not equal. Short jump.	3	4
CJNE Rn,#data,rel	Compares immediate data to the register and jumps if not equal. Short jump.	3	4
CJNE @Ri,#data,rel	Compares immediate data to indirect register and jumps if not equal. Short jump.	3	4
DJNZ Rn,rel	Decrements register and jumps if not 0. Short jump.	2	3
DJNZ Rx,rel	Decrements direct byte and jump if not 0. Short jump.	3	4
NOP	No operation	1	1

Data Transfer Instructions

Data transfer instructions move the content of one register to another. The register the content of which is moved remains unchanged. If they have the suffix “X” (MOVX), the data is exchanged with external memory.

DATA TRANSFER INSTRUCTIONS
Mnemonic	Description	Byte	Cycle
MOV A,Rn	Moves the register to the accumulator	1	1
MOV A,direct	Moves the direct byte to the accumulator	2	2
MOV A,@Ri	Moves the indirect RAM to the accumulator	1	2
MOV A,#data	Moves the immediate data to the accumulator	2	2
MOV Rn,A	Moves the accumulator to the register	1	2
MOV Rn,direct	Moves the direct byte to the register	2	4
MOV Rn,#data	Moves the immediate data to the register	2	2
MOV direct,A	Moves the accumulator to the direct byte	2	3
MOV direct,Rn	Moves the register to the direct byte	2	3
MOV direct,direct	Moves the direct byte to the direct byte	3	4
MOV direct,@Ri	Moves the indirect RAM to the direct byte	2	4
MOV direct,#data	Moves the immediate data to the direct byte	3	3
MOV @Ri,A	Moves the accumulator to the indirect RAM	1	3
MOV @Ri,direct	Moves the direct byte to the indirect RAM	2	5
MOV @Ri,#data	Moves the immediate data to the indirect RAM	2	3
MOV DPTR,#data	Moves a 16-bit data to the data pointer	3	3
MOVC A,@A+DPTR	Moves the code byte relative to the DPTR to the accumulator (address=A+DPTR)	1	3
MOVC A,@A+PC	Moves the code byte relative to the PC to the accumulator (address=A+PC)	1	3
MOVX A,@Ri	Moves the external RAM (8-bit address) to the accumulator	1	3-10
MOVX A,@DPTR	Moves the external RAM (16-bit address) to the accumulator	1	3-10
MOVX @Ri,A	Moves the accumulator to the external RAM (8-bit address)	1	4-11
MOVX @DPTR,A	Moves the accumulator to the external RAM (16-bit address)	1	4-11
PUSH direct	Pushes the direct byte onto the stack	2	4
POP direct	Pops the direct byte from the stack/td>	2	3
XCH A,Rn	Exchanges the register with the accumulator	1	2
XCH A,direct	Exchanges the direct byte with the accumulator	2	3
XCH A,@Ri	Exchanges the indirect RAM with the accumulator	1	3
XCHD A,@Ri	Exchanges the low-order nibble indirect RAM with the accumulator	1	3

Logic Instructions

Logic instructions perform logic operations upon corresponding bits of two registers. After execution, the result is stored in the first operand.

LOGIC INSTRUCTIONS
Mnemonic	Description	Byte	Cycle
ANL A,Rn	AND register to accumulator	1	1
ANL A,direct	AND direct byte to accumulator	2	2
ANL A,@Ri	AND indirect RAM to accumulator	1	2
ANL A,#data	AND immediate data to accumulator	2	2
ANL direct,A	AND accumulator to direct byte	2	3
ANL direct,#data	AND immediae data to direct register	3	4
ORL A,Rn	OR register to accumulator	1	1
ORL A,direct	OR direct byte to accumulator	2	2
ORL A,@Ri	OR indirect RAM to accumulator	1	2
ORL direct,A	OR accumulator to direct byte	2	3
ORL direct,#data	OR immediate data to direct byte	3	4
XRL A,Rn	Exclusive OR register to accumulator	1	1
XRL A,direct	Exclusive OR direct byte to accumulator	2	2
XRL A,@Ri	Exclusive OR indirect RAM to accumulator	1	2
XRL A,#data	Exclusive OR immediate data to accumulator	2	2
XRL direct,A	Exclusive OR accumulator to direct byte	2	3
XORL direct,#data	Exclusive OR immediate data to direct byte	3	4
CLR A	Clears the accumulator	1	1
CPL A	Complements the accumulator (1=0, 0=1)	1	1
SWAP A	Swaps nibbles within the accumulator	1	1
RL A	Rotates bits in the accumulator left	1	1
RLC A	Rotates bits in the accumulator left through carry	1	1
RR A	Rotates bits in the accumulator right	1	1
RRC A	Rotates bits in the accumulator right through carry	1	1

Bit-oriented Instructions

Similar to logic instructions, bit-oriented instructions perform logic operations. The difference is that these are performed upon single bits.

BIT-ORIENTED INSTRUCTIONS
Mnemonic	Description	Byte	Cycle
CLR C	Clears the carry flag	1	1
CLR bit	Clears the direct bit	2	3
SETB C	Sets the carry flag	1	1
SETB bit	Sets the direct bit	2	3
CPL C	Complements the carry flag	1	1
CPL bit	Complements the direct bit	2	3
ANL C,bit	AND direct bit to the carry flag	2	2
ANL C,/bit	AND complements of direct bit to the carry flag	2	2
ORL C,bit	OR direct bit to the carry flag	2	2
ORL C,/bit	OR complements of direct bit to the carry flag	2	2
MOV C,bit	Moves the direct bit to the carry flag	2	2
MOV bit,C	Moves the carry flag to the direct bit	2	3

** Explain 8051 addressing modes.

The CPU can access data in various ways. i.e in a register or in memory or be provided as an immediate value. These various ways of accessing data are called addressing modes.

The 8051 provides a total of five addressing modes. They are

1. Immediate addressing mode

2. Register addressing mode

3. Direct addressing mode

4. Register indirect addressing mode

5. Indexed addressing mode

Immediate addressing mode :

In immediate addressing mode an 8/16 bit immediate data/constant is specified in the instruction itself.

The immediate data must be express as pound sign i.e #.

This addressing mode is used to load information into any of the register including the DPTR register.

We can also use immediate addressing mode to send data to 8051 ports.

Eg: MOV P₁ , # 55H

When 8051 executes an immediate data , program counter is automatically incremented.

Eg: MOV A, #25H

MOV R₄, # 65H

MOV DPTR , # 4654H

MOV DPL, #45H

MOV DPH , #88H

Register addressing mode :

In Register addressing mode, the instruction will specify the name of register as a operand. In register addressing mode, registers A, DPTR and R₀ to R₇ are used in the part of a mnemonic as source or destination.

Eg: MOV A,R₀

MOV A,R₇

ADD A, R₅

We can move the data between accumulator and R_n registers. But data will not move in between R_n registers.

Eg : MOV R₄, R₇ is invalid.

Direct addressing mode :

In direct addressing mode, the address of the data is directly specified in the instruction. The direct address can be the address of an internal data RAM location (00H to 7FH) or address of a special function register (80H to FFH0

Eg : MOV R₀, 40H

MOV 0E0H, # 55H or MOV A, # 55H

MOV 0E0H, R₂

MOV 56H, A

The SFR can be accessed by the names or by their addresses.

The major use of direct addressing mode is the stack. In 8051 family, only direct addressing mode is allowed for pushing onto the stack. Therefore “PUSH A” instruction is invalid.

Pushing the accumulator onto the stack must be coded as “PUSH 0E0H” . Similarly pushing R₃ of bank 0 is coded as “PUSH 03”.

For the POP instruction to POP the top of the stack into R₄ of bank 0 we use “POP 04” instruction.

Register indirect addressing mode :

In the register indirect addressing mode, a register is used as a pointer to the data. If the data is inside the CPU, only registers R₀ & R₁ are used as pointers then they must be preceded by the @ sign, to address only for the internal RAM locations ( 00H to FFH ) . The external RAM can be addressed indirectly through DPTR.

Looping is not possible in direct addressing mode. & It is possible in Indirect addressing mode.

Eg: MOV A, @ R₀

MOV @R₁ , B

Indexed addressing mode:

Indexed addressing mode is widely used in accessing data elements of look-up table entries located in the program ROM space of the 8051.

The instruction used for this purpose is MOV A, @A+DPTR.

The 16-bit register DPTR and register A are used to form the address of the data element stored in on-chip ROM.

Because the data elements are stored in the program (code) space ROM of the 8051. The instruction MOVC is used instead of MOV . The C means code.

In this instruction the contents of A are added to the 16-bit register DPTR to form the 16-bit address of the needed data.

Timers / Counters

8051 has two 16-bit programmable UP timers/counters. They can be configured to operate either as timers or as event counters. The names of the two counters are T0 and T1 respectively. The timer content is available in four 8-bit special function registers, viz, TL0,TH0,TL1 and TH1 respectively.

In the "timer" function mode, the counter is incremented in every machine cycle. Thus, one can think of it as counting machine cycles. Hence the clock rate is 1/12^th of the oscillator frequency.

In the "counter" function mode, the register is incremented in response to a 1 to 0 transition at its corresponding external input pin (T0 or T1). It requires 2 machine cycles to detect a high to low transition. Hence maximum count rate is 1/24 ^th of oscillator frequency.

The operation of the timers/counters is controlled by two special function registers, TMOD and TCON respectively.

Timer Mode control (TMOD) Special Function Register:

TMOD register is not bit addressable.

TMOD
Address: 89 H

Various bits of TMOD are described as follows -

Gate: This is an OR Gate enabled bit which controls the effect of on START/STOP of Timer. It is set to one ('1') by the program to enable the interrupt to start/stop the timer. If TR1/0 in TCON is set and signal on pin is high then the timer starts counting using either internal clock (timer mode) or external pulses (counter mode).

It is used for the selection of Counter/Timer mode.
Mode Select Bits:

M1 and M0 are mode select bits.

Timer/ Counter control logic:

Fig 8.1 Timer/Counter Control Logic

Timer control (TCON) Special function register:

TCON is bit addressable. The address of TCON is 88H. It is partly related to Timer and partly to interrupt.

Fig 8.2 TCON Register

The various bits of TCON are as follows.

TF1 : Timer1 overflow flag. It is set when timer rolls from all 1s to 0s. It is cleared when processor vectors to execute ISR located at address 001BH.
TR1 : Timer1 run control bit. Set to 1 to start the timer / counter.
TF0 : Timer0 overflow flag. (Similar to TF1)
TR0 : Timer0 run control bit.
IE1 : Interrupt1 edge flag. Set by hardware when an external interrupt edge is detected. It is cleared when interrupt is processed.
IE0 : Interrupt0 edge flag. (Similar to IE1)
IT1 : Interrupt1 type control bit. Set/ cleared by software to specify falling edge / low level triggered external interrupt.
IT0 : Interrupt0 type control bit. (Similar to IT1)
As mentioned earlier, Timers can operate in four different modes. They are as follows

Timer Mode-0:

In this mode, the timer is used as a 13-bit UP counter as follows.

Fig. 8.3 Operation of Timer on Mode-0

The lower 5 bits of TLX and 8 bits of THX are used for the 13 bit count.Upper 3 bits of TLX are ignored. When the counter rolls over from all 0's to all 1's, TFX flag is set and an interrupt is generated.

The input pulse is obtained from the previous stage. If TR1/0 bit is 1 and Gate bit is 0, the counter continues counting up. If TR1/0 bit is 1 and Gate bit is 1, then the operation of the counter is controlled by input. This mode is useful to measure the width of a given pulse fed to input.

Timer Mode-1:

This mode is similar to mode-0 except for the fact that the Timer operates in 16-bit mode.

Fig 8.4 Operation of Timer in Mode 1

Timer Mode-2: (Auto-Reload Mode)

This is a 8 bit counter/timer operation. Counting is performed in TLX while THX stores a constant value. In this mode when the timer overflows i.e. TLX becomes FFH, it is fed with the value stored in THX. For example if we load THX with 50H then the timer in mode 2 will count from 50H to FFH. After that 50H is again reloaded. This mode is useful in applications like fixed time sampling.

Fig 8.5 Operation of Timer in Mode 2

Timer Mode-3:

Timer 1 in mode-3 simply holds its count. The effect is same as setting TR1=0. Timer0 in mode-3 establishes TL0 and TH0 as two separate counters.

Fig 8.6 Operation of Timer in Mode 3

Control bits TR1 and TF1 are used by Timer-0 (higher 8 bits) (TH0) in Mode-3 while TR0 and TF0 are available to Timer-0 lower 8 bits(TL0).

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